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International CMOS Technology
Commercial/ Industrial
PEELTM 18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device
Features
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Multiple Speed Power, Temperature Options - VCC = 5 Volts 10% - Speeds ranging from 5ns to 25 ns - Power as low as 37mA at 25MHz - Commercial and industrial versions available CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs Development / Programmer Support - Third party software and programmers - ICT PLACE Development Software and PDS-3 programmer - PLD-to-PEEL JEDEC file translator
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Architectural Flexibility - Enhanced architecture fits in more logic - 74 product terms x 36 input AND array - 10 inputs and 8 I/O pins - 12 possible macrocell configurations - Asynchronous clear - Independent output enables -- 20 Pin DIP/SOIC/TSSOP and PLCC
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Application Versatility - Replaces random logic - Super sets PLDs (PAL, GAL, EPLD) - Enhanced Architecture fits more logic than ordinary PLDs
General Description
The PEEL18CV8 is a Programmable Electrically Erasable Logic (PEEL) device providing an attractive alternative to ordinary PLDs. The PEEL18CV8 offers the performance, flexibility, ease of design and production practicality needed by logic designers today. The PEEL18CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP packages with speeds ranging from 5ns to 25ns with power consumption as low as 37mA. EE-Reprogrammability provides the convenience of instant reprogramming for development and reusable production inventory minimizing the impact of programming changes or errors. EE-Reprogrammability also improves factory testability, thus assuring the highest quality possible. The PEEL18CV8 architecture allows it to replace over 20 standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also provides additional architecture features so more logic can be put into every design. ICT's JEDEC file translator instantly converts to the PEEL18CV8 existing 20-pin PLDs without the need to rework the existing design. Development and programming support for the PEEL18CV8 is provided by popular third-party programmers and development software. ICT also offers free PLACE development software and a low-cost development system (PDS-3).
Figure 1 Pin Configuration
I/CLK I I I I I I I I GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC I/O I/O I/O I/O I/O I/O I/O I/O I
Figure 2 Block Diagram
DIP
TSSOP
PLCC
SOIC
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PEELTM 18CV8
Figure 3 PEEL18CV8 Logic Array Diagram
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PEELTM 18CV8
array. (Note that PEEL device programmers automatically program all of the connections on unused product terms so that they will have no effect on the output function).
Function Description
The PEEL18CV8 implements logic functions as sum-ofproducts expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. Userconfigurable output structures in the form of I/O macrocells further increase logic flexibility.
Programmable I/O Macrocell
The unique twelve-configuration output macrocell provides complete control over the architecture of each output. The ability to configure each output independently permits users to tailor the configuration of the PEEL18CV8 to the precise requirements of their designs.
Architecture Overview
The PEEL18CV8 architecture is illustrated in the block diagram of Figure 2. Ten dedicated inputs and 8 I/Os provide up to 18 inputs and 8 outputs for creation of logic functions. At the core of the device is a programmable electricallyerasable AND array which drives a fixed OR array. With this structure, the PEEL18CV8 can implement up to 8 sumof-products logic expressions. Associated with each of the 8 OR functions is an I/O macrocell which can be independently programmed to one of 12 different configurations. The programmable macrocells allow each I/O to create sequential or combinatorial logic functions of active-high or active-low polarity, while providing three different feedback paths into the AND array.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 4, consists of a Dtype flip-flop and two signal-select multiplexers. The configuration of each macrocell is determined by the four EEPROM bits controlling these multiplexers. These bits determine output polarity, output type (registered or nonregistered) and input-feedback path (bidirectional I/O, combinatorial feedback). Refer to Table 1 for details. Equivalent circuits for the twelve macrocell configurations are illustrated in Figure 5. In addition to emulating the four PAL-type output structures (configurations 3,4,9, and 10), the macrocell provides eight additional configurations. When creating a PEEL device design, the desired macrocell configuration generally is specified explicitly in the design file. When the design is assembled or compiled, the macrocell configuration bits are defined in the last lines of the JEDEC programming file.
AND/OR LOGIC ARRAY
The programmable AND array of the PEEL18CV8 (shown in Figure 3) is formed by input lines intersecting product terms. The input lines and product terms are used as follows:
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36 Input Lines: - 20 input lines carry the true and complement of the signals applied to the 10 input pins - 16 additional lines carry the true and complement values of feedback or input signals from the 8 I/Os 74 product terms: - 64 product terms (arranged in groups of 8) are used to form sum of product functions - 8 output enable terms (one for each I/O) - 1 global synchronous preset term - 1 global asynchronous clear term
Output Type
The signal from the OR array can be fed directly to the output pin (combinatorial function) or latched in the D-type flipflop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register will be set HIGH at the next rising edge of the clock input. Satisfying the asynchronous clear will set Q LOW, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset.
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At each input-line/product-term intersection, there is an EEPROM memory cell that determines whether or not there is a logical connection at that intersection. Each product term is essentially a 36-input AND gate. A product term that is connected to both the true and complement of an input signal will always be FALSE and thus will not affect the OR function that it drives. When all the connections on a product term are opened, a "don't care" state exists and that term will always be TRUE. When programming the PEEL18CV8, the device programmer first performs a bulk erase to remove the previous pattern. The erase cycle opens every logical connection in the array. The device is configured to perform the user-defined function by programming selected connections in the AND
Output Polarity
Each macrocell can be configured to implement active-high or active-low logic. Programmable polarity eliminates the need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled under the control of its associated programmable output enable product term. When the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the I/O pin. Otherwise, the output buffer is switched into the high-impedance state. Under the control of the output enable term, the I/O pin can
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PEELTM 18CV8
Registered Feedback
Feedback also can be taken from the register, regardless of whether the output function is to be combinatorial or registered. When implementing a combinatorial output function, registered feedback allows for the internal latching of states without giving up the use of the external output.
function as a dedicated input, a dedicated output, or a bidirectional I/O. Opening every connection on the output enable term will permanently enable the output buffer and yield a dedicated output. Conversely, if every connection is intact, the enable term will always be logically false and the I/O will function as a dedicated input.
Input/Feedback Select
The PEEL18CV8 macrocell also provides control over the feedback path. The input/feedback signal associated with each I/O macrocell may be obtained from three different locations; from the I/O input pin, from the Q output of the flip-flop (registered feedback), or directly from the OR gate (combinatorial feedback).
Design Security
The PEEL18CV8 provides a special EEPROM security bit that prevents unauthorized reading or copying of designs programmed into the device. The security bit is set by the PLD programmer, either at the conclusion of the programming cycle or as a separate step, after the device has been programmed. Once the security bit is set it is impossible to verify (read) or program the PEEL until the entire device has first been erased with the bulk-erase function.
Bi-directional I/O
The input/feedback signal is taken from the I/O pin when using the pin as a dedicated input or as a bi-directional I/O. (Note that it is possible to create a registered output function with a bi-directional I/O.)
Programming Support
ICT's JEDEC file translator allows easy conversion of existing 20 pin PLD designs to the PEEL18CV8, without the need for redesign. ICT supports a broad range of popular third party design entry systems, including Data I/O Synario and Abel, Logical Devices CUPL and others. ICT also offers (for free) its proprietary PLACE software, an easy-touse entry level PC-based software development system. Programming support includes all the popular third party programmers; Data I/O, Logical Devices, and numerous others. ICT also provides a low cost development programmer system, the PDS-3.
Combinatorial Feedback
The signal-select multiplexer gives the macrocell the ability to feedback the output of the OR gate, bypassing the output buffer, regardless of whether the output function is registered or combinatorial. This feature allows the creation of asynchronous latches, even when the output must be disabled. (Refer to configurations 5,6,7 and 8 in Figure 5.)
Figure 4 Block Diagram of the PEEL18CV8 I/O Macrocell
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PEELTM 18CV8
Configuration #
1 2 3 4 5 6 7 8 9 10 11 12
A
1 0 1 0 1 0 1 0 1 0 1 0
B
1 1 0 0 1 1 0 0 1 1 0 0
C
1 1 1 1 1 1 1 1 0 0 0 0
D
1 1 1 1 0 0 0 0 0 0 0 0
Input/Feedback Select
Bi-directional I/O Bi-directional I/O Bi-directional I/O Bi-directional I/O Combinatorial Feedback Combinatorial Feedback Combinatorial Feedback Combinatorial Feedback Register Feedback Register Feedback Register Feedback Register Feedback Register Register
Output Select
Active Low Active High Active Low Active High Active Low Active High Active Low Active High Active Low Active High Active Low Active High
Combinatorial Combinatorial Register Register Combinatorial Combinatorial Register Register Combinatorial Combinatorial
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PEELTM 18CV8
This device has been designed and tested for the specified operating ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage.
Absolute Maximum Ratings Symbol
VCC VI, VO IO TST TLT
Parameter
Supply Voltage Voltage Applied to Any Pin Output Current Storage Temperature Lead Temperature
2
Conditions
Relative to Ground Relative to Ground Per Pin (IOL, IOH)
1
Rating
-0.5 to + 6.0 -0.5 to VCC + 0.6 25 -65 to +150
Unit
V V mA C C
Soldering 10 Seconds
+300
Operating Range Symbol
Vcc TA TR TF TRVCC
Parameter
Supply Voltage Commercial Industrial Commercial Industrial See Note 3. See Note 3. See Note 3.
Conditions
Min
4.75 4.5 0 -40
Max
5.25 5.5 +70 +85 20 20 250
Unit
V V C C ns ns ms
Ambient Temperature Clock Rise Time Clock Fall TIme VCC Rise Time
D.C. Electrical Characteristics Over the operating range (Unless otherwise specified) Symbol
VOH VOHC VOL VOLC VIH VIL IIL IIP IIH ISC9
Parameter
Output HIGH Voltage - TTL Output HIGH Voltage - CMOS Output LOW Voltage - TTL Output LOW Voltage - CMOS 12 Input HIGH level Input LOW Voltage Input, I/O Leakage Current LOW Input and I/O pull-ups disabled Input, I/O Leakage Current LOW Input and I/O pull-ups enabled Input, I/O Leakage Current HIGH Output Short Circuit Current
12
Conditions
VCC = Min, IOH = -4.0 mA VCC = Min, IOH = -10 A VCC = Min, IOL = 16mA/24mA 13 VCC = Min, IOL = 10 A
Min
2.4 VCC - 0.3
Max
Unit
V V
0.5 0.15 2.0 -0.3 VCC + 0.3 0.8 -10 -100 0 (Typical) -30 -5 40 -135 90 90 110/115 45/55 37/50 6 12
V V V V A A A mA
VCC = Max, VIN = GND, I/O = High Z VCC = Max, VIN = GND, I/O = High Z VCC = Max, VIN = VCC, I/O = High Z VCC = 5V, VO = 0.5V, TA = 25C
ICC10
VCC Current, f=1MHz
VIN = 0V or VCC, f = 25 MHz All Outputs disabled4
-7 -10 -15 -25
mA
CIN7 COUT7
Input Capacitance Output Capacitance
TA = 25C, VCC = 5.0V @ f = 1 MHz
pF pF
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A.C. Electrical Characteristics
Over the operating range 8
Symbol
tPD tOE tOD tCO1 tCO2
tCF tSC tHC tCL, tCH tCP fMAX1 fMAX2 fMAX3 tAW tAP tAR tRESET
5 5
Parameter
Input5 to non-registered output Input to output enable
6 6
-5 -7 -10/I-10 -15/I-15 -25/I-25 Units Min Max Min Max Min Max Min Max Min Max
5 5 5 4 7.5 2.5 3.5 0
8
7.5 7.5 7.5 7 10 3.5 5 0 3.5 12 117.6 83.3 142.8 7.5 5 0 5 12 111 83.3 100 10 7.5 7.5 5
10 10 10 7 12 4 12 0 10 24 50 41.6 50 15 10 10 5
15 15 15 12 25 8 20 0 15 35 28.5 28.5 33.3 25 15 15 5
25 25 25 15 35 15
ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns
Input to output disable Clock to Output
Clock to comb. output delay via internal registered feedback Clock to Feedback Input5 or feedback setup to clock Input hold after clock Clock low time, clock high time
5
3 7 166.7 133 166.7 5 5 5 5
Min clock period Ext (tSC + tCO1) Internal feedback (1/tSC+tCF) External Feedback (1/tCP)11 No Feedback (1/tCL+tCH) 11 Asynchronous Reset Pulse Width Input to Asynchronous Reset Asynchronous Reset recovery time Power-on reset time for registers in clear state
5 11
25 25 5
ns ns s
Switching Waveforms
Inputs, I/O, Registered Feedback, Synchronous Preset Clock Asynchronous Reset Registered Outputs Combinatorial Outputs
Notes:
1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V for periods less than 20 ns. 2. VI and VO are not specified for program/verify operation. 3. Test Points for Clock and VCC in tR and tF are referenced at the 10% and 90% levels. 4. I/O pins are 0V and VCC. 5. "Input" refers to an input pin signal. 6. tOE is measured from input transition to VREF0.1V, TOD is measured from input transition to VOH-0.1V or VOL+0.1V; VREF=VL. 7. Capacitances are tested on a sample basis. 8. Test conditions assume: signal transition times of 3ns or less from the 10% and 90% points, timing reference levels of 1.5V (Unless otherwise specified). 9. Test one output at a time for a duration of less than 1 second. 10. ICC for a typical application: This parameter is tested with the device programmed as an 8-bit Counter. 11. Parameters are not 100% tested. Specifications are based on initial characterization and are tested after any design process modification that might affect operational frequency. 12. Available only for 18CV8 -15/I-15/-25/I-25 grades 13. 24mA available for 18CV8-5/-7. All other speeds are 16mA.
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PEELTM 18CV8
PEEL Device and Array Test Loads
Standard Load 5V Thevenin Equivalent VL
R1 Output Output
RL
CL
R2
CL
Technology
CMOS12 TTL -10/-15/-25 TTL -5/-7
R1
480k 235 159
R2
480k 159 118
RL
228k 95 68
VL
2.375V 2.02V 2.129V
CL
33 pF 33 pF 33 pF
Ordering Information Part Number
PEEL18CV8J-5 PEEL18CV8P-7 PEEL18CV8J-7 PEEL18CV8S-7 PEEL18CV8P-10 PEEL18CV8PI-10 PEEL18CV8J-10 PEEL18CV8JI-10 PEEL18CV8S-10 PEEL18CV8SI-10 PEEL18CV8T-10 PEEL18CV8TI-10 PEEL18CV8P-15 PEEL18CV8PI-15 PEEL18CV8J-15 PEEL18CV8JI-15 PEEL18CV8S-15 PEEL18CV8SI-15 PEEL18CV8T-15 PEEL18CV8TI-15 PEEL18CV8P-25 PEEL18CV8PI-25 PEEL18CV8J-25 PEEL18CV8JI-25 PEEL18CV8S-25 PEEL18CV8SI-25 PEEL18CV8T-25 PEEL18CV8TI-25
Speed
5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns 10 ns 15 ns 15 ns 15 ns 15 ns 25 ns 25 ns 25 ns 25 ns
Temperature
Commercial Commercial Commercial Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Package
20-pin Plastic (J) Leaded Chip Carrier (PLCC) 20-pin Plastic 300 mil DIP 20-pin Plastic (J) Leaded Chip Carrier (PLCC) 20-pin SOIC 20-pin Plastic 300 mil DIP 20-pin Plastic (J) Leaded Chip Carrier (PLCC) 20-pin SOIC 20-pin TSSOP 170 mil 20-pin Plastic 300 mil DIP 20-pin Plastic (J) Leaded Chip Carrier (PLCC) 20-pin SOIC 20-pin TSSOP 170 mil 20-pin Plastic 300 mil DIP 20-pin Plastic (J) Leaded Chip Carrier (PLCC) 20-pin SOIC 20-pin TSSOP 170 mil
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PEELTM 18CV8
Part Number
Device Suffix PEEL18CV8 PI-25 Speed -5 = 5ns tPD -7 = 7.5ns tPD -10 = 10ns tPD -15 = 15ns tPD -25 = 25ns tPD Temperature Range (Blank) = Commercial 0 to +70C I = Industrial -40 to +85 C
Package P = 20-pin Plastic 300mil DIP J = 20-pin Plastic (J) Leaded Chip Carrier (PLCC) S = 20-pin SOIC 300 mil Gullwing T = 20-pin TSSOP 170 mil
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PEELTM 18CV8
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